Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits
نویسنده
چکیده
The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic circuits based on timing critical paths, and is further extended through a process variation aware circuit level timing optimization algorithm for dynamic CMOS circuits. Implemented on a 64-b adder and ISCAS benchmark circuits for mixed-static-dynamic CMOS, the design level optimization algorithm demonstrated a critical path delay improvement of over 52% in comparison with static CMOS implementation by state-of-the-art commercial optimization tools.
منابع مشابه
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations
| Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the non-inverting nature of the logic and the complex timing relationships associated with the clock scheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitionin...
متن کاملDynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-dynamic CMOS logic, wher...
متن کاملComparative Analysis of Static and Dynamic CMOS Logic Design
The choice of the CMOS logic to be used for implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. This paper presents a comparative study of CMOS static and dynamic logic. Effect of voltage variation on power and delay of static and dynamic CMOS logic styles studied. The performance of static ...
متن کاملProcess-Variation-Resistant Dynamic Power Optimization for VLSI Circuits
Introduction Introduction Background Background – – Dynamic power dissipation Dynamic power dissipation – – Glitch reduction Glitch reduction – – Previous LP model Previous LP model Process Process-variation variation-resistant LP model resistant LP model – – Process variation Process variation – – Delay model Delay model – – LP model based on worst LP model based on worst-case timing case timi...
متن کاملDesign of a Low Power Magnetic Memory in the Presence of Process Variations
With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and t...
متن کامل